May 2011

The complexity for minimum component costs has increased at a rate of roughly a factor of two per year... [T]here is no reason to believe it will not remain nearly constant for at least 10 years... Perhaps newly devised design automation procedures could translate from logic diagram to technological realization without any special engineering.”

Gordon E. Moore
Electronics, April 19, 1965


The electronic design automation (EDA) tool industry is big business, and commercial licenses are extremely expensive. Open standards have driven many proprietary EDA technologies to be publicly released as free/libre open source software (F/LOSS) and some have become IEEE standards. Competition has partly given way to collaboration and has led to these standards. The development path of important EDA tools frequently now employs F/LOSS practices, which have overcome resistance to collaborative innovation between competing businesses. F/LOSS technologies are at the vanguard of leading-edge system-on-chip (SoC) design, not just because they are free, but also because they are valuable.

The first commercial integrated circuits (ICs), designed by hand, helped guide manned space flight to the moon on the Apollo missions. In the past decade, silicon IP firms have shown they are limited only by their ideas, not by limited investment opportunities, and SoC firms have shown they can greatly reduce costs while innovating on the development of the largest new IC designs. This high-end technology is made accessible to startups because of open source. It is no longer just for mega-corporations.

This article reviews the history of key advances in ICs and EDA tools. The common theme presented in this article for the driver of technology innovation is the requirement to develop the most advanced microprocessor possible. Today, a low-cost, high-value-added business model can efficiently serve the market for IC subsystems licensed as intellectual property (silicon IP) in the form of compilable source code. Alternatively, for larger SoC designs, engineering budgets can be shifted from the purchase of a relatively small number of high-cost EDA tool licenses to open source EDA technologies that can be run on massive compute-server farms. The two business models are not theoretical, but realistic. The author explains how his company (Crack Semiconductor) developed commercially successful cryptographic silicon IP using entirely open source EDA technologies and how another company (SiCortex) pushed the limits of IC design and open source EDA tools by simulating and verifying a massively parallel supercomputer.


In 1965, Gordon E. Moore was Director of Fairchild Semiconductor's R&D laboratories and made his famous observation, as quoted above, that would become known as "Moore's Law". At that time, ICs were closely coupled to rocket science (figuratively and literally), and microprocessors had not yet been invented. Fairchild was then busy supplying the first commercial ICs for the Apollo Guidance Computer. This computer was used on the successful moon missions, and it helped bring Apollo 13 back home. Thousands of Fairchild ICs, containing only a NOR gate with three transistors each, were used to build one system. It would take more than twenty years and billions of dollars worth of industrial R&D to achieve Moore's prediction of EDA tools that could “translate from logic diagrams to technological realization without any special engineering”.

In 1968, Gordon Moore and Robert Noyce founded Intel, a classic Silicon Valley startup, which in 1971 produced the first microprocessor (uP) design. This first microprocessor contained 2300 transistors. Intel uP transistor counts grew to 820 million in 35 years, a 2.07 times increase every two years. Moore's Law was coined by Carver Mead, professor of VLSI design at Caltech, in reference to Moore's prediction of the growth rate of IC designs in his now-famous 1965 Electronics article.

By the mid-1980s, a more efficient alternative to logic diagrams appeared: software-like hardware description languages (HDLs) that model concurrent logic circuit activity. The US Air force required the complete logic functional description of a digital IC. This requirement led to the open language specification called VHDL. Proprietary logic simulation technology helped fuel the growth of the commercial IC industry. As a business strategy to counter VHDL's gains in market share, the dominant language (Verilog) was later released to an independent organization so it could be developed as an open specification. Ironically, both VHDL and Verilog have become IEEE standards managed by the same organization, now called Accellera.

Proprietary logic design and simulation tool projects, for almost 50 years, have been supported within vertically integrated mega-corporations, and they, like the tools, have prospered and withered. Several EDA and IC startups flourished to become mega-corporations themselves, but many failed and quietly faded away. IC companies (such as Intel), telecommunications R&D labs (such as Bell-Northern Research, or BNR), and computer giants (such as IBM and Digital Equipment Corporation, or DEC), all developed internal EDA tools to support their own chip designs. Later, a robust EDA industry formed as engineers left large companies to start new firms.

In the next section, we discuss the emergence of the silicon IP business model and how proprietary tools have given some way to F/LOSS tools. In the last section, we show that F/LOSS tools can help silicon IP business founders avoid dilution of their shares in the company and loss of control before the idea is turned into an important innovation. They can also support the economical trade-off of expensive tool licenses versus computing resources. An example of each is given: F/LOSS tools enabled the author to develop commercially successful cryptographic silicon IP, and the extreme limits of IC design were pushed by simulating and verifying a massively parallel supercomputer.

The Emergence of the Silicon IP Business Model

In this section, the development of the microprocessor is used as the common design element. The silicon IP business model is shown to have been preceded first by the vertically organized, fabricating semiconductor company. The fabless semiconductor company outsourced IC fabrication and so required vastly smaller investment capital, but each business type still designed everything "in-house". Design teams were large and significant financial resources required venture capital to be raised. At a critical moment, design tools enabled highly productive and much smaller design teams, and the microprocessor concept took a leap forward with the introduction of the reduced instruction set compute (RISC) as a core of silicon IP that was licensed without ever having been manufactured. This was followed by the introduction of the programmable logic chip, and finally, F/LOSS design tools that enable silicon IP startups to design, test, and deliver working IC designs with almost no capital investment beyond their intellectual contributions.

Long before the silicon IP business model emerged to fill the current market need, microprocessors were designed by very large high-technology businesses. These companies were often vertically integrated by necessity. This led to the development of internal EDA technologies that predated equivalent commercial offerings. An advanced technology company owned its own IC design and manufacturing processes, and its internal tool development programs were closely coupled to those processes. Examples include IBM's "Einstimer" tool for checking if the chip signals meet timing requirements and BNR's "Funsim" hardware design simulator.

The vertically integrated "semiconductor fabrication-oriented" business model was joined by the "fabless" semiconductor startup, which was enabled by the availability of commercial EDA tools. The fabless semiconductor company - clearly viable in the mid-1990s - now could design all the logic functions required in an application-specific IC (ASIC), without needing a manufacturing capability. The ASIC design could then be manufactured by a semiconductor foundry, called the "fab". But, relentlessly, IC designs have grown by Moore's Law. It is now quite impractical for one company to design all the logic functions in the chip, so the silicon IP market now supplies a significant ratio of the functional logic to a company that integrates these subsystems on an SoC.

The classic IC microprocessor that was designed and manufactured by one company started to face competition in the 1990s. ARM Ltd., which started as Acorn Computers and was joined later by Apple and VLSI Technologies, developed the silicon IP business model by introducing a small, but powerful reduced instruction set computer (RISC) design to be licensed to other companies that would embed the silicon IP into their IC design. Embedded RISC processors are used in virtually all of today's hot products, such as smart phones and tablets. By 2008, over 10 billion ARM processors were licensed. ARM's initial success as a silicon IP vendor in the microprocessor market demonstrated that massive industrial resources are not required for the silicon IP business model. ARM proved that small design teams - even one individual - can produce valuable processor designs as silicon IP.

A final plank in the silicon IP business model platform is the field programmable gate array (FPGA). The FPGA has allowed Moore's prophetic call for "design automation procedures [that] could translate from logic diagram to technological realization without any special engineering" to be realized. The two leading FPGA vendors, Xilinx and Altera, provide low-cost or free tools to automatically convert HDL source code to a device-specific technology, place it on the pre-manufactured chip, and wire up the components in minutes.

From Proprietary EDA Tools to F/LOSS Solutions

Initially, silicon IP vendors had little option but to acquire expensive EDA tool licenses where each simulator might cost, for example, $25,000. This need usually forced the founders to give up equity to fund their innovations. Now with F/LOSS tools for EDA, innovators can develop their advanced silicon IP, and with FPGA technology, the silicon IP vendor can let a potential customer evaluate the IP in their own design for very low cost and risk.

The emergence of an F/LOSS suite of EDA tools for the front-end logic design and verification has followed an interesting path. In this section, the requirement for a technology that would allow software and hardware to be modeled and simulated is described. Two problems drove this movement to open source EDA tools; one is technical and the other is business-oriented, concerning how competitors can collaborate. As a secondary effect, open source technologies have enabled the low-cost silicon IP startup as a viable business to supply both real designs and models to enable faster and higher-quality solutions. These technologies have liberated the silicon IP business model from its dependence on highly diluting venture capital.

The technical problem to be solved can be summarized by the following question: How can complex microprocessor designs execute software, given that the interaction between software and hardware must be well understood before the design is committed to silicon? This concept is called co-simulation. The competitor's problem was to determine how the business can profit if it shares its advanced EDA tool innovations with its competitor.

In the 1990s, the need for a co-simulation technology lead DEC to develop Verilator - discussed in greater detail below - purely for DEC's internal use. DEC's misfortune has lead to other's fortune, because Verilator is now the leading F/LOSS tool for the silicon IP startup on a micro-budget. The demands for even higher system-level co-simulation and modeling technology led to SystemC as a collaborative effort between EDA companies. Verilator and SystemC form the "killer app" for silicon IP startups.

Extreme engineering challenges confront leading-edge IC development projects. Internal innovation is often the only option to overcome a technical limitation of a commercial EDA tool. However, with access to the source code, a feature can be added or a bug can be fixed directly.

The microprocessor IC is typically so complex that many simulations of its operation are required to verify the design. Requirements led to capabilities that frequently could only be developed by internal EDA tool development teams working closely with the processor designers. Most vertically integrated companies funded (and many continue to fund) internal EDA tool development and had proprietary design flows. Industry standardization was regarded by leading-edge companies, frequently correctly, as imposing a step down in capability. Processor designs were often far more advanced than the logic devices that could be designed and manufactured with commercial EDA tools, and they often pushed those tools past the breaking point. Arguably, the internal tools of Intel, IBM, DEC, and BNR were the crown jewels of each corporation. But this common practice of internal development also led to wasteful duplication and resistance to external ideas and innovations, which were ignored because the were "not invented here".

Many companies today are choosing to collaborate with their competition on the development of fundamental technologies by supporting F/LOSS EDA initiatives. However, this is not so in the case of DEC against Intel.

Intel is now a dominant microprocessor IC company, but many companies vied for the position, including IBM, AMD, and DEC. Intel only emerged as the dominant processor vendor after it began its “Wintel” collaboration with Microsoft. DEC's innovation for its Alpha processor is a good case study. To verify the Alpha, DEC developed the tool called Verilator starting in 1994. The requirement was to co-simulate C (software code) and Verilog (hardware code) together. Verilog was “verilated” to C for DEC's Alpha uP project and then compiled with a C compiler. In 1998, nearing the end of a long run, DEC publicly released the source code for Verilator before the company was sold to Compaq. Since 2001, Verilator has been maintained by Wilson Snyder.

Processor design is now more complex than ever, and silicon IP cannot be developed following the writing of detailed design specifications for both software and hardware. This takes too long and correct designs emerge from frequent, short iteration cycles using first models and then more detailed modules. So, leading edge EDA companies decided to collaborate by forming the Open SystemC Initiative. By collaborating in the specification of the SystemC language and its later extensions, these companies assured that a stable market for their value-added co-simulation and modeling design tools would exist.

Silicon IP Developed With Verilator and SystemC

The author's company, Crack Semiconductor, recently licensed to a large European client an RSA public key cryptographic security processor to accelerate banking security transactions. Crack Semiconductor's RSA processor optimally multiplies numbers that are enormous: 1024-bits and larger. The IP was developed in Verilog and was verilated to SystemC, and then was compiled with G++ for simulation. A SystemC test environment generated random numbers, which were used as a basis for an external function call to pre-compute system constants and the expected results using GNU bc, an arbitrary precision calculator language. The SystemC test then read the expected results from a file, programmed the virtual processor, and executed the simulation of the verilated RSA processor. During development, when results were incorrect, bc scripts were written to compute intermediate results to compare against the values generated by the 32-bit multiplier, or at any other selected observation point in the processor. There are no commercial tools available to do this kind of “specialized engineering”. Finally, for delivery to the client, free synthesis tools offered by Xilinx were used to convert the soft IP core to a technology-specific format used by the client.

Technology innovation in IC design methodologies often triggers new ideas for F/LOSS EDA tools that will support the next generation of IC designs. Wilson Snyder was a member of the development team that designed the 972-node parallel SiCortex supercomputer. The 200 million transistor SiCortex chip contains 64-bit RISC processors that represents one “node” in the supercomputer, and was developed using the same basic technology used by Crack Semiconductor. The SiCortex team exploited all manner of open source technologies to enable up to four hundred Linux compute servers to run simulations in parallel and report what aspects of the test plan have been covered. This new open source technology is called CovVise. CovVise is not just one technology, but actually leverages a wide variety of F/LOSS technologies generally referred to as LAMP (Linux operating system, Apache web server, MySQL database, and Perl/PHP scripting language). A commercial Verilog simulator license has a list price around $25,000, so economically, Verilator, SystemC, and CovVise represents a compelling solution for large IC design teams.


On the 46th anniversary of Gordon E. Moore's seminal paper in Electronic, F/LOSS EDA tools enable logic descriptions to be technologically realized without any special engineering, as Moore predicted. Front-end design engineering of silicon IP still requires extremely specialized engineering problem-solving efforts, and usually commercial tools do not fully address the problems that arise. Engineers at the cutting edge of technological development routinely must invent new design and verification tools, and F/LOSS is indispensable in this effort.

All manner of business models are receptive to F/LOSS EDA tools. From silicon IP startups with micro-budgets to large corporations like NXP (Philips Semiconductor), many companies use these tools today. They do save money by using F/LOSS, but they do not use them just because they are free of monetary cost. They use them because they are valuable. From DEC to SiCortex and Crack Semiconductor, open source Verilator, combined with IEEE Standard SystemC and SystemPerl, offers compelling value for silicon IP startups.

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